The present invention relates to a memory device which is backed up by a backup power supply when a main power supply is interrupted.
Hitherto, among random access memories (RAMS) for use as the memory devices of microcomputers and the like, some RAMS using CMOS memory elements have been known. This CMOS memory element is used as a pseudo nonvolatile memory in many cases because its electric power consumption is very low and data can be held for a long time by the data holding voltage from a backup power supply. Therefore, by connecting a chargeable Ni-Cd battery or the like to the CMOS memory elements as a backup power supply, the CMOS memory elements can produce data holding characteristics similar to a real nonvolatile memory.
The memory device using such CMOS memory elements needs to check whether the memory contents are correctly held in the memory device or not when the main power supply is recovered after the elapse of a certain period of time after the main power supply was interrupted due to, for example, a power failure or the like. Conventionally, as one of those checking methods, there has been known the following method. Namely, a predetermined special collating code is stored in a part of the RAM composed of the CMOS memory elements and the collating code stored in the read only memory (ROM). The collating code is read out from the RAM and compared with the collating code stored in the ROM when the main power supply is recovered and the reset signal is released. If those collating codes coincide, it is determined that the memory contents stored in the other memory areas in the RAM are correct.
When using the aforementioned method whereby the collating code is stored in a part of the RAM for the memory device using the CMOS memory elements constituted as explained above, the memory contents can be determined to be correct by comparison with that collating code. But, since the collating codes cannot be stored in all areas of the RAM, it is impossible to determine that all the memory contents of the RAM are correct.
In addition, when the power supply of the main power supply unit to supply the driving voltage to the RAM is interrupted due to a power failure or the like, the backup power supply is connected to the RAM by a switching circuit, thereby supplying the data holding voltage of the backup power supply to the RAM. On the other hand, in the case where the driving voltage which is supplied to the control section such as a central processing unit (CPU) or the like to execute the writing and readout of information in and from the RAM drops to the allowable lower limit voltage, a reset signal is generally produced from a reset signal generator provided for the main power supply unit. When the CPU receives the reset signal, it stops all operations. However, since an output voltage detector for producing a switch control signal to drive the switching circuit and the reset signal generator are independently provided, the timing when the reset signal is generated and the operation timing of the switching circuit can deviate.
Therefore, in the case where the reset signal was generated after the power supply voltage to the RAM had been switched to the data holding voltage from the main power supply voltage due to the operation of the switching circuit, there is a risk that the CPU will execute the storing operation in the RAM for the interval of time from when the driving signal for the switching circuit was generated until the reset signal is generated. In such a case, there is a chance that erroneous data will be stored or that the data to be stored is not stored.